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Synopsis
This book provides insight into the behavior and design of power distribution systems for high speed, high complexity integrated circuits. Also presented are criteria for estimating minimum required on-chip decoupling capacitance. Techniques and algorithms for computer-aided design of on-chip power distribution networks are also described; however, the emphasis is on developing circuit intuition and understanding the principles that govern the design and operation of power distribution systems.
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From the Back Cover
Power Distribution Networks with On-Chip Decoupling Capacitors is dedicated to distributing power in high speed, high complexity integrated circuits with power levels exceeding tens of watts and the power supply below a volt. The book provides insight and intuition into the behavior and design of integrated circuit-based power distribution systems.
The book has three primary objectives. The first is to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the power terminals of the on-chip circuitry. The second is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. The third objective is to present design methodologies for effciently placing on-chip decoupling capacitors in nanoscale integrated circuits.
Power Distribution Networks with On-Chip Decoupling Capacitors is a reference for professional engineers in the fields of circuits and systems and computer-aided design.
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