This revised, updated and expanded text deals mainly with techniques used in uniprocessor architectures to attain high performance. Many of these techniques involve some form of parallelism, which is hidden from the user. Developments in the Cray and Cyber 205 architectures are detailed and new material is included on array architectures, using the DAP as a case study and on multiprocessor architectures using C.mmp, the butterfly and the transputer as examples. The material is designed to accompany undergraduate courses in computer architecture and constitute a core of material presented in third and fourth year courses in the Computer Science Department at Edinburgh University.
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Seller: Better World Books Ltd, Dunfermline, United Kingdom
Condition: Very Good. 2nd Revised edition. Pages intact with possible writing/highlighting. Binding strong with minor wear. Dust jackets/supplements may not be included. Stock photo provided. Product includes identifying sticker. Better World Books: Buy Books. Do Good. Seller Inventory # 53321363-20
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Seller: Better World Books Ltd, Dunfermline, United Kingdom
Condition: Good. 2nd Revised edition. Former library copy. Pages intact with minimal writing/highlighting. The binding may be loose and creased. Dust jackets/supplements are not included. Includes library markings. Stock photo provided. Product includes identifying sticker. Better World Books: Buy Books. Do Good. Seller Inventory # GRP63115843
Quantity: 2 available