Synopsis
A description of the development of a parallel computer of the single instruction-stream, multiple data-stream (SIMD) class. It is a type of SIMD computer known as a processor-array and the computer described here is known as the reconfigurable processor-array or RPA. For simple operations a large array of bit-serial processing elements is a better source of processing power than a small array of complex processors, and the RPA described here is enhanced with floating-point, multiplication and data cache facilities to improve the operation of such arrays. The RPA also has features which allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism. The implementation of the architecture as a chip deisgn, for possible VLSI realization, is described, and the appendix contains a high-level formal description of the processing element in a register-transfer language.
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