Timing Verification of Application-Specific Integrated Circuits (ASICs) (Prentice Hall Modern Semiconductor Design Series' Sub Series)

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9780137943487: Timing Verification of Application-Specific Integrated Circuits (ASICs) (Prentice Hall Modern Semiconductor Design Series' Sub Series)

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79434-7

It's About Time

In today's high-speed designs, timing analysis is critical to success. This is the first book to focus exclusively on these crucial timing issues, with special emphasis on timing verification of ASICs. Timing Verification of Application Specific Integrated Circuits (ASICs) highlights principles and techniques over specific tools. This method makes the materials applicable to a variety of logic design approaches, especially in the field of deep submicron digital design. Topics include:

  • Clock definitions, multicycle paths, false paths, and phase-locked loops
  • Behavioral and structural RTL coding for timing
  • Timing analysis of FPGAs
  • Pre and Post layout timing analysis
  • Synthesis and Timing constraints
  • EDA timing tools

Numerous design examples and Verilog codes offer practical illustrations of all the concepts. Timing Verification of Application Specific Integrated Circuits (ASICs) is a must for all logic designers concerned with the accuracy of timing and clock issues.

About the Author:

FARZAD NEKOOGAR, formerly a Technical Manager at Intrinsix Corp., has extensive practical experience verifying timing of ASICs, FPGAs, and systems-on-a-chip. He is a lecturer at the University of California at Davis, and is the author of "Digital Control Using Digital Signal Processing, " published by Prentice Hall PTR.

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Book Description Lebanon, Indiana, U.S.A.: Prentice Hall, 1999. Soft cover. Book Condition: New. Dust Jacket Condition: New. 1st Edition. **INTERNATIONAL EDITION** Read carefully before purchase: This book is the international edition in mint condition with the different ISBN and book cover design, the major content is printed in full English as same as the original North American edition. The book printed in black and white, generally send in twenty-four hours after the order confirmed. All shipments contain tracking numbers. Great professional textbook selling experience and expedite shipping service. Bookseller Inventory # ABE-8050483639

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Book Description Prentice Hall, 1999. Book Condition: New. Brand New, Unread Copy in Perfect Condition. A+ Customer Service! Summary: 1. Introduction to Timing Verification. Introduction. Overview of Timing Verification. Interface Timing Analysis. 2. Elements of Timing Verification. Introduction. Clock Definitions. More on STA. Timing Analysis of Phase-Locked Loops. 3. Timing in ASICs. Introduction. Prelayout Timing. Postlayout Timing. ASIC Sign-Off Checklist. 4. Programmable Logic Based Design. Introduction. Programmable Logic Structures. Design Flow. Timing Parameters. Timing Analysis. HDL Synthesis. Software Development Systems. A. PrimeTime. B. Pearl. C. TimingDesigner. D. Transistor-Level Timing Verification. References. Index. About the Author. Bookseller Inventory # ABE_book_new_0137943482

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