Introductory VHDL: From Simulation To Synthesis

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9780131378438: Introductory VHDL: From Simulation To Synthesis

This book focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises, and tutorials are provided for the use of the new integrated design environments from Xilinx—which is available with the book. For engineers interested in Digital Design Laboratory, Digital Design, Advanced Digital Design, and Advanced Digital Logic

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From the Inside Flap:


Good judgement comes from experience
Experience comes from bad judgement

It is often pointed out that some things are best learned by "doing" and that the use of computer-aided design (CAD) tools in the design of digital systems is one such body of knowledge. Over the years, hardware description languages have evolved to aid in the description, modeling, and design of digital systems. The steady advances in microelectronics continues to increase the power and complexity of digital systems, which in turn places increasing demands on the associated CAD environments. Early in the next century silicon die are projected to pack in excess of one billion transistors. At the forefront of modern systems research are methodologies for the design of systems composed of these billion transistor chips. The intellectual capacity of human designers is limited and has led to the use of the principles of hierarchy, abstraction, and modularity in handling the increasing complexity of digital systems. The semiconductor industry's continued relentless march towards increasing densities and speeds will only increase the designers reliance on design tools to manage the complexity of future designs. Hardware description languages such as VHDL (VHSIC Hardware Description Language) form an integral part of such design environments.

My earlier book, VHDL Starters Guide, focused on the use of VHDL as a language for describing digital systems for the purpose of simulation in tasks such as performance evaluation and design verification. This book attempts to expand that point of view to encompass the use of a VHDL description as a point of departure for the synthesis of digital hardware. The emergence of an IEEE Standard for VHDL and the rapid development and use of the IEEE Standard VHDL language in industry makes it imperative that we provide opportunities for electrical and computer engineering students to learn the language and become proficient in its application both in simulation and synthesis environments.

There are many excellent books on the VHDL language and its use for the purpose of building accurate models of complex digital systems. These books have been largely complete treatments of the language and generally have been written for practicing engineers, and more recently for use in graduate and undergraduate courses. In the last few years the use of hardware description languages in the undergraduate classroom has become more common; it is no longer unusual for students to use VHDL or Verilog in their junior or senior design projects.

Even with all these developments in education, I find the usage of hardware descriptions languages in the classroom for the purposes of synthesis at the same point that I found the treatment of simulation modeling five years ago. Texts that treat the synthesis of digital hardware from high-level language descriptions focus on the intellectually challenging problem of synthesis from abstract specifications, whether they are executable language specifications or other formal specifications. Thus, courses dealing with synthesis tend to be at the advanced graduate level. At the same time introductory digital logic courses make use of synthesis tools for Boolean expressions and state machines. The courses may start from prior generation specification languages or even a hardware description language such as VHDL and will target programmable logic arrays and the rapidly expanding area of field programmable gate arrays (FPGAs). The focus on synthesis in this book is motivated by the rapid growth of FPGAs in all manner of digital systems from low-cost controllers to high-speed special purpose co-processors. It is my belief that FPGAs will become a mainstay in the digital designers tool chest, and synthesis from high-level languages will be a dominant design methodology. Hence I foresee a need for the integration of FPGAs into courses in digital logic and computer architecture.

This text is not intended to be a comprehensive coverage of the VHDL language. Rather, it is intended to provide an introduction to the basic language concepts, and a framework for thinking about the structure and operation of VHDL programs from the point of view of modeling and simulation as well as synthesis. The book introduces key VHDL constructs that are motivated by the behavioral and physical properties of digital systems. Each language construct is studied from two opposing points of view: i) for the purpose of simulation the physical or behavioral attribute of a digital system that is captured by the language construct and ii) for the purposes of synthesis the digital hardware that is implied by the construct.

Programming idioms from conventional programming languages by themselves are insufficient for productively learning to apply hardware description languages such as VHDL. Through laboratory exercises, students can very quickly come up to speed in building useful, non-trivial models of digital systems. As their experience grows, so will their need for more comprehensive information and modeling techniques, which can be found in a variety of existing textbooks and the standard language reference manual.

This book is intended to support a first look at the language and as such I have decided to focus on what I felt were the most commonly used aspects of the language. VHDL has often been accused of being bulky, overly complicated, and difficult to use. Although the language may possess a large number of features I have found that I can focus on a core set of language constructs that can enable to students to rapidly become productive in its application. By packaging the Xilinx Foundation CAD tools with this text I hope students will be provided with a productive learning experience. Intended Audience

The style of the book is motivated by the need for a text for sophomore- through senior-level texts used in courses in digital logic, computer architecture, and capstone design projects. The ability to construct simulation models of, or synthesize, the building blocks studied in these courses is an invaluable teaching aid.

Students learn the most about digital systems if they have to build them, in this case using VHDL models. I have found it valuable in my own courses to provide concurrent laboratory exercises that reinforce foundational material taught in the classroom. The scope and complexity of hardware laboratory exercises are limited by the available time in a semester- or quarter-long course. The VHDL language provides an opportunity for students to experiment with larger designs than would be feasible in a hardware laboratory, using a development environment that is rapidly being adopted throughout the industrial community. In the case of VHDL I like an approach that enables students to adjust quickly to the basic language concepts such that they could construct models of basic logic and computer architecture components productively in sophomore- and junior-level courses. The full power of the language is not necessary at this point, nor should it be. As students progress to more advanced courses and their needs grow, they will be able to use productively the more advanced language features and their corresponding texts as references. Style of the Book

VHDL is a complex language that could easily be worthy of a course in its own right. However, curricula are usually strapped for credit hours, and devoting a course to teach VHDL would mean eliminating existing material from the curricula. The style of this book is intended to permit integration of the basic concepts underlying VHDL into existing courses without necessitating additional credit hours or courses for instruction. In order to fill the need for a companion text for digital logic and computer architecture courses and to serve as an early introduction to the basic language concepts the book must satisfy several criteria. First, it must relate VHDL concepts to those already familiar to the student. Students learn best when they can relate new concepts to ones that are already familiar to them. In this case we rely on concepts from the operation of digital circuits. Language features are motivated by the need to describe specific aspects of the operation of digital circuits, for example, events, propagation delays, and concurrency. Second, each language feature must be accompanied by examples. Simulation exercises address one or more VHDL modeling concepts. To keep with the idea of a companion book, tutorials for two VHDL environments are provided in the Appendices. Finally, the text must be prescriptive. Chapter 4, Chapter 6, and Chapter 8 each provide a prescription for writing classes of VHDL models. This is not intended to produce the most efficient models, but serves the purpose of rapidly bringing the student to a point where he or she can construct useful simulation models for instructional purposes. By enabling a look at the detailed operation of digital systems, VHDL reinforces the foundational concepts taught in the classroom. At this point, students begin to think about alternative, more creative, and often more efficient approaches to constructing the models.

This book, Introductory VHDL: From Simulation to Synthesis, attempts to develop an intuitive and structured way of thinking about VHDL models without necessarily spending a great deal of time on advanced language features. Students should be able to learn enough quickly through exercises and association with classroom concepts to be able to construct useful models with the help of this book. During development, portions of Introductory VHDL: From Simulation to Synthesis have been utilized in a two-course sequence on computer architecture at Georgia Tech. Sophomore students typically start with no background in VHDL but with a good background in high-level programming languages such as C or Pascal. By the end of, the second quarter they will have built a model of a pipelined RISC processor with hazard detection, data forwarding, and branch prediction. Early in the second quarter the students make the transition from knowing VHDL as a new language to knowing how to use it as a tool for studying computer architecture. The goal is to integrate VHDL into the curriculum early in a manner that strengthens the learning of the concepts while concurrently providing training in the use of VHDL simulation tools.

The approach I take in this book is a bit unusual in that I do not begin with a discussion and presentation of language syntax and constructs, that is, identifiers, operators, and so forth. In fact, the book presents core constructs via examples and the syntax is not presented until late in the text with the notion that this chapter will be used more as a reference. The premise is that readers who have had experience with programming in high-level languages simply need an accurate syntactic reference to these language constructs. I believe that the road to building useful models is built on an understanding of how we can describe those aspects of hardware systems that require constructs that are not typically found in traditional programming language definitions, such as signals and the concept of time; this is where the bulk of this book is focused. As a result, a syntactic reference to the core programming language features has been reduced to a single chapter. My goal is to focus on the concepts underlying the VHDL language. If I can capture the novel features of the language in a manner that appeals to the reader's intuition and is based on thinking in hardware or systems terms, then a reference to the syntax of core constructs is sufficient to get students started in building useful models. My hope is that this text can apply this approach successfully and fulfill the goal of getting students at the sophomore level excited about the use of such languages in general and the evolving design methodologies in particular. Once they have reached this goal, they are then capable of more rapidly expanding their understanding to the full scope of the language. Organization of the Text

As a result of this view, the text starts with concepts from the operation of digital circuits. This text assumes that the reader is comfortable with introductory digital logic and programming in a block-structured, high-level language such as Pascal or C. The subsequent chapters introduce various VHDL constructs. Each set of language constructs are first introduced as representations of the operational and physical attributes of digital systems. Then the same set of language constructs are discussed from the point of view of inferring digital circuit implementations that correspond to the behavior captured by the language construct. This dual interpretation is carried on throughout the text as new language constructs are introduced. For example Chapter 4 and Chapter 5 discuss basic language constructs from the point of view of simulation and synthesis respectively. Though VHDL is often criticized as a bulky and complex language in its entirety, the associations between language features and digital are intuitive and therefore easy to pick up. Once the basic concepts are understood a good syntactic reference to the language is sufficient for the students to be able to build models quickly of digital circuits including higher-level objects such as register files, ALUs, and simple datapaths.

Chapter 4, Chapter 6, and Chapter 8 provide recipes for building basic VHDL models. These models are not necessarily the most efficient but are intuitive and easy to get students started. Each of these chapters provide simulation exercises that can be exercised by the student to reinforce the concepts. Chapter 5, Chapter 7, and a part of Chapter 8 discuss the construction of models from the point of view of synthesis. The concepts are reinforced by exercises.

Completion of the exercises provides the student with an ability to proceed to more complex language features and productive use of any of the existing comprehensive VHDL language texts. In our curriculum, the students proceed to senior design projects where they describe systems in VHDL, synthesize their designs, and emulate the resulting designs using hardware emulators. Chapter 9 through Chapter 12 present language features as additional functionality that serve a specific purpose, for example, input-output and procedures. A syntactic reference to the common language features is provided in Chapter 12.

Several appendices have been added to support the material in the text. For example, a tutorial for the Xilinx Foundation tools and a tutorial for Aldec's Active VHDL simulator are provided. Another appendix provides a detailed template for a VHDL model illustrating the relative ordering of program constructs. This can serve as a handy reference toward the end of the student's experience. A third appendix provides a description of a model of the SPIM processor datapath described in "Computer Organization & Design: The Hardware Software Interface" by D. Patterson and J. Hennessey 9. Students in a first-quarter architecture course can modify this datapath by adding instructions or modifying the controller to implement a more complex state machine. A fourth appendix provides a synthesizable model of a pipelined version of t...

From the Back Cover:

The book has been written to introduce students and practitioners alike to two important topics:

  • Basic VHDL language concepts
  • A framework for thinking and reasoning about the structure and operation of VHDL programs when modeling for simulation and synthesis.

The road to useful models is paved by language features motivated by the need to describe behavioral and physical properties of digital circuits such as events, propagation delays, and concurrency. In this book, each major language construct is studied from two points of view:

  • For the purpose of the simulation of physical or behavioral attributes of a digital system
  • For the purpose of synthesis of the digital hardware

Each language feature presented in the book is accompanied by a complete example. Simulation and synthesis exercises address one or more associated VHDL modeling concepts. Further, the book is packaged with the Xilinx Student Edition Foundation Series Software, producing a powerful and self-contained learning environment. The result of reading this book is a fast paced ascension through the language to productive applications for solving realistic problems.

Practicing engineers will find the text and tool application self-paced. Instructors will find that the style of the book enables it to be used as a companion to courses in digital logic, computer architecture, or a HDL course. The Xilinx Student Edition tool sets enable students to quickly develop intuition about VHDL models. All readers will progress rapidly from reading to creating functioning models.

By focusing on the most commonly used core constructs and providing tutorials with the accompanying Xilinx Student Edition tools, Introductory VHDL: From Simulation To Synthesis is a must for those wishing to rapidly add VHDL to their skill sets.

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