Formal Verification: An Essential Toolkit for Modern VLSI Design - Softcover

Seligman, Erik; Schubert, Tom; Kumar, M V Achutha Kiran

Softcover

ISBN 10: 0128007273 ISBN 13: 9780128007273

Publisher: Morgan Kaufmann, 2015

Synopsis

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.

About this title

Review:

"...the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation...I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification..." --VerificationAcademy.com

Review:

Intel insiders demystify formal verification to improve circuit design and increase productivity

About this edition

• Publisher: Morgan Kaufmann
• Publication date: 2015
• ISBN 10: 0128007273
• ISBN 13: 9780128007273
• Binding: Paperback
• Number of pages: 372