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Published by Springer, 2013
ISBN 10: 9400737270ISBN 13: 9789400737273
Seller: booksXpress, Bayonne, NJ, U.S.A.
Book
Soft Cover. Condition: new.
Published by Springer, 2013
ISBN 10: 9400737270ISBN 13: 9789400737273
Seller: Lucky's Textbooks, Dallas, TX, U.S.A.
Book
Condition: New.
Published by Springer, 2013
ISBN 10: 9400737270ISBN 13: 9789400737273
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Book Print on Demand
Condition: New. PRINT ON DEMAND Book; New; Fast Shipping from the UK. No. book.
Published by Springer 2013-11, 2013
ISBN 10: 9400737270ISBN 13: 9789400737273
Seller: Chiron Media, Wallingford, United Kingdom
Book
PF. Condition: New.
Published by Springer Netherlands Nov 2013, 2013
ISBN 10: 9400737270ISBN 13: 9789400737273
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Book Print on Demand
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design. 184 pp. Englisch.
Published by Springer Netherlands, 2013
ISBN 10: 9400737270ISBN 13: 9789400737273
Seller: moluna, Greven, Germany
Book Print on Demand
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. This is the first comprehensive book on Adiabatic Logic systemsIt presents how Adiabatic Logic will perform with future scaling, future devices and degrading effectsIt presents measurement results of a manufactured adiabatic system and comp.
Published by Springer Netherlands, 2013
ISBN 10: 9400737270ISBN 13: 9789400737273
Seller: AHA-BUCH GmbH, Einbeck, Germany
Book
Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.