Guan Liang Wen Jia Zhang (1 results)

paperback. Condition: New. Ship out in 2 business day, And Fast shipping, Free Tracking number will be provided after the shipment.Paperback. Pub Date: December 2012 Pages: 180 Language: Chinese Publisher: Tsinghua University Press in Higher Education in electronic information planning textbook: EDA technology and applications Altera Corporation EPIC3 FPGA modeled details internal structure and functional design of EPIC3 Altera FPGA design tools Quartus II design and VHDL hardware description language. and the analysis of the corresponding instance. the instance of the design and expansion of the three aspects of mental training. guide the reader can quickly grasp the FPGA design methodology and design concept. through training gradually increase the level of their own design. With exercises at the end of each chapter. the easy readers learning and teaching use. National ordinary the universities electronic information planning textbook: EDA technology and applications institutions of higher learning electronic engineering. communications. industrial automation. computer application technology disciplines undergraduate or graduate electronic design or EDA technology courses can be used as teaching materials and experimental The guide book as a reference book of professional and technical personnel. Contents: Chapter 1 Introduction 1.1 PLD Classification 1.2 PLD design process 1.2.1 Design input 1.2.2 design comprehensive 1.2.3 simulation 1.2.4 Design verify 1.3 PLD design commonly used tools 1.3.1 1.2.5 download Altera Corporation design and development tools 1.3.2 Xilinx design and development tools 1.4 PLD technology trends Exercises Chapter 2 EPIC3 type FPGA architecture 2.1 logic array block 2.1.1 LAB 2.2.1 LUT chain connection 2.1.2 LAB control signal 2.2 logical unit and register the chain 2.2.2 addnsub signal Path Interconnect 2.3.1 line mode of operation over 2.3 2.2.3 LE 2.4.2 Parity bit support shift 2.4.3 Interconnect 2.3.2 column interconnect of 2.4 embedded memory 2.4.1 memory mode register support 2.4.4 memory size configuration 2.4.5 byte able to the 2.4.6 control signal and M4K Interface 2.4.7 independent clock mode 2.4.8 Input / output clock mode 2.4.9 read / write clock mode 2.4.10 single port mode 2.5 global clock networks and phase-locked loop 2.5.1 global clock network 2.5.2 dual-purpose clock pin 2.5.3 combination of resources 2.5.4 Phase Locked Loop 2.5.5 clock multiplier and divider 2.5.6 external clock input external clock output 2.5.8 2.5.7 clock feedback 2.5.9 2.5.10 lock detection signal programmable duty cycle 2.5.11 2.5.12 control signal phase shift 2.6 input / output structure 2.6.1 external RAM interface 2.6.2 DDR SDRAM and FCRAM2.6.3 programmable drive capability 2.6.4 programmable pull-up resistor 2.7 IEEE Standard 1149.1 (JTAG) boundary scan support exercises in Chapter 3. based on the design of the the Quartus FPGA design method 3.1 Quartus software input 3.1.1 Text Editor 3.1 .2 module and Symbol Editor 3.1.3 MegaWizard Plugin Manager 3.1.4 Quartus support other design input 3.2 Quartus software design constraints 3.2.1 Assignment Editor 3.2.2 Pin Planner 3.2.3 Settings dialog box . Chapter 5 Chapter 4 VHDL hardware description language FPGA design examples ReferencesFour Satisfaction guaranteed,or money back.