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- PublisherLAP LAMBERT Academic Publishing
- Publication date2019
- ISBN 10 6139463122
- ISBN 13 9786139463121
- BindingPaperback
- Number of pages68
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Shared Hardware Accelerator for Hybrid AHt-MPSoC Architecture
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LAP LAMBERT Academic Publishing Mrz 2019
(2019)
ISBN 10: 6139463122
ISBN 13: 9786139463121
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Book Description Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In this system, there is presented a new class of hybrid AHt-MPSoC architecture in which hardware accelerators are shared between processors in such a way that to reduce system cost and increase performance. A novel hybrid memory scheme is proposed by this scheme is assessed through extensive simulation to show significant improvements in performance. Hybrid Asymmetric heterogeneous MPSoC architecture consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell in association to Hardware Accelerator (HWA) shared methodology to determine the common computational tasks in between the concurrent tasks of application. An experimental result shows that the proposed hybrid AHt-MPSoC system power consumption reduced from the existing system and their area/performance tradeoffs evaluated very quickly. 68 pp. Englisch. Seller Inventory # 9786139463121
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Shared Hardware Accelerator for Hybrid AHt-MPSoC Architecture : Research Perspective
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LAP LAMBERT Academic Publishing
(2019)
ISBN 10: 6139463122
ISBN 13: 9786139463121
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Book Description Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In this system, there is presented a new class of hybrid AHt-MPSoC architecture in which hardware accelerators are shared between processors in such a way that to reduce system cost and increase performance. A novel hybrid memory scheme is proposed by this scheme is assessed through extensive simulation to show significant improvements in performance. Hybrid Asymmetric heterogeneous MPSoC architecture consists of a Static Random Access Memory (SRAM) and an embedded Dynamic Random Access Memory (eDRAM) cell in association to Hardware Accelerator (HWA) shared methodology to determine the common computational tasks in between the concurrent tasks of application. An experimental result shows that the proposed hybrid AHt-MPSoC system power consumption reduced from the existing system and their area/performance tradeoffs evaluated very quickly. Seller Inventory # 9786139463121
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Shared Hardware Accelerator for Hybrid AHt-MPSoC Architecture
Published by
LAP LAMBERT Academic Publishing
(2019)
ISBN 10: 6139463122
ISBN 13: 9786139463121
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Book Description Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Prasath R. ArunDr. R. Arun Prasath, Professor in the Department of ECE at Siddhartha Institute of Technology & Science,Telangana. Received his Ph.D in ICE from Anna University, Chennai. He possess 10 plus years of experience in teach. Seller Inventory # 284372285
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