Design for High Performance, Low Power, and Reliable 3D Integrated Circuits - Hardcover

Lim, Sung Kyu

Hardcover

ISBN 10: 1441995412 ISBN 13: 9781441995414

Publisher: Springer, 2012

Synopsis

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits This book describes a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It provides full details of all key algorithms, for maximum understanding and utility.

About this title

From the Back Cover:

This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process.

• Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability.
• Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs.
• Covers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance.
• Includes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements.

About this edition

• Publisher: Springer
• Publication date: 2012
• ISBN 10: 1441995412
• ISBN 13: 9781441995414
• Binding: Hardcover
• Number of pages: 588