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Synopsis
Learn to model for synthesis using VHDL. See the details of how VHDL gets translated into logic gates in this book. Also, see how hardware elements are described in synthesizable VHDL. This book is a must primer for anyone who is beginning to learn synthesis using VHDL. A chapter on verification explains the many causes of simulation mismatches between pre and post synthesis models and how to avoid these. Modeling guidelines are also provided to help improve synthesis results.
"synopsis" may belong to another edition of this title.
- PublisherStar Galaxy Publishing
- Publication date2011
- ISBN 10 0984629211
- ISBN 13 9780984629213
- BindingPaperback
- LanguageEnglish
- Number of pages316
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A VHDL Synthesis Primer, Second Edition
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Star Galaxy Publishing, 2011
ISBN 10: 0984629211
ISBN 13: 9780984629213
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