Interconnect Analysis and Synthesis - Hardcover

Cheng, Chung-Kuan; Lillis, John; Lin, Shen; Chang, Norman

Hardcover

ISBN 10: 0471293660 ISBN 13: 9780471293668

Publisher: Wiley-Interscience, 1999

Synopsis

State-of-the-art methods and current perspectives on interconnect The irrepressible march toward smaller and faster integrated circuits has made interconnect a hot topic for semiconductor research. The effects of wire size, topology construction, and network design on system performance and reliability have all been thoroughly investigated in recent years. Interconnect Analysis and Synthesis provides CAD researchers and engineers with powerful, state-of-the-art tools for the analysis, design, and optimization of interconnect. It brings together a wealth of information previously scattered throughout the literature, explaining in depth available analysis techniques and presenting a range of CAD algorithms for synthesizing and optimizing interconnect. Along with examples and results from the semiconductor industry and 150 illustrations, this practical work features:

• Models for interconnect as well as devices and the impact of scaling trends
• Modern analysis techniques, from matrix reduction and moment matching to transmission-line analysis
• An overview of the effects of inductance on on-chip interconnect
• Flexible CAD algorithms that can be generalized for different needs, from buffer insertion to wire sizing to routing topology
• Emphasis on realistic problem formulations, addressing key design tradeoffs such as those between area and performance

About this title

About the Author

Chung-Kuan Cheng is the author of Interconnect Analysis and Synthesis, published by Wiley.

John Lillis is the author of Interconnect Analysis and Synthesis, published by Wiley.

Shen Lin is the author of Interconnect Analysis and Synthesis, published by Wiley.

Norman Chang is the author of Interconnect Analysis and Synthesis, published by Wiley.

From the Back Cover

State-of-the-art methods and current perspectives on interconnect The irrepressible march toward smaller and faster integrated circuits has made interconnect a hot topic for semiconductor research. The effects of wire size, topology construction, and network design on system performance and reliability have all been thoroughly investigated in recent years. Interconnect Analysis and Synthesis provides CAD researchers and engineers with powerful, state-of-the-art tools for the analysis, design, and optimization of interconnect. It brings together a wealth of information previously scattered throughout the literature, explaining in depth available analysis techniques and presenting a range of CAD algorithms for synthesizing and optimizing interconnect. Along with examples and results from the semiconductor industry and 150 illustrations, this practical work features:
* Models for interconnect as well as devices and the impact of scaling trends
* Modern analysis techniques, from matrix reduction and moment matching to transmission-line analysis
* An overview of the effects of inductance on on-chip interconnect
* Flexible CAD algorithms that can be generalized for different needs, from buffer insertion to wire sizing to routing topology
* Emphasis on realistic problem formulations, addressing key design tradeoffs such as those between area and performance

Excerpt. © Reprinted by permission. All rights reserved.

Interconnect Analysis and Synthesis

By Chung-Kuan Cheng John Lillis Shen Lin Norman Chang

JOHN WILEY & SONS

Copyright © 2000 John Wiley & Sons, Inc.
All right reserved.
ISBN: 978-0-471-29366-8

Contents

Preface..........................................................................xiAcknowledgments..................................................................xiii1 Introduction...................................................................11.1 Overview.....................................................................11.2 Book Organization............................................................22 Interconnect Models............................................................52.1 Technology Trends............................................................52.2 Device and Interconnect Scaling..............................................62.3 Interconnect Models..........................................................102.4 The Effect of Capacitive Coupling............................................222.5 The Effect of Inductive Coupling.............................................302.6 Transmission Line Model......................................................332.7 Power Dissipation............................................................342.8 Interconnect Reliability.....................................................343 Device Models..................................................................393.1 Introduction.................................................................393.2 Device I-V Characteristics...................................................393.3 General Format of Device Models..............................................413.4 Device Models in Explicit Expression.........................................423.5 Device Model Using a Table-Lookup Model......................................433.6 Effective Capacitance Model..................................................454 Interconnect Analysis..........................................................514.1 Introduction.................................................................514.2 Time Domain Analysis.........................................................524.3 S Domain Analysis............................................................564.4 Circuit Reduction via Matrix Approximation...................................594.5 Analysis Using Moment Matching...............................................684.6 Transmission Lines...........................................................855 Inductance and Inductive Coupling for On-Chip Interconnect.....................995.1 Introduction.................................................................995.2 On-Chip Inductance Consideration.............................................1255.3 On-Chip Design Solutions to Cope with Inductance Effects.....................1455.4 Summary......................................................................1576 Synthesis: Overview and Static Topology Optimization...........................1616.1 Introduction.................................................................1616.2 Overview of Interconnect Synthesis...........................................1626.3 Optimization of Static Routing Topologies....................................1706.4 Summary, Discussion, and Further Reading.....................................1896.5 Exercises....................................................................1907 Global Routing Topology Synthesis..............................................1937.1 Introduction.................................................................1937.2 Background and Overview......................................................1937.3 Preliminaries................................................................1967.4 Finding High-Quality Sink Permutations.......................................1997.5 Tree Construction for a Given Permutation....................................2027.6 Experiments..................................................................2117.7 Summary and Comments.........................................................2167.8 Further Reading..............................................................2197.9 Exercises....................................................................2208 Optimization of Multisource Nets...............................................2238.1 Introduction.................................................................2238.2 Preliminaries and Formulations...............................................2258.3 Linear Time Computation of ARD T Under Elmore................................2278.4 The Repeater Insertion Algorithm.............................................2298.5 Summary, Discussion, and Further Reading.....................................2388.6 Exercises....................................................................2399 Timing-Driven Maze Routing.....................................................2419.1 Introduction.................................................................2419.2 Assumptions..................................................................2429.3 Formulations.................................................................2439.4 Algorithms...................................................................2459.5 A Label-Setting Refinement...................................................2479.6 Example......................................................................2489.7 An Algorithm for Formulation 9.2.............................................2529.8 Incorporating Buffer Insertion...............................................2539.9 Complexity...................................................................2549.10 Summary and Comments........................................................2559.11 Exercises...................................................................257Index............................................................................259

Preface

Our main goal in writing this book was to present a physical-design oriented perspective on contemporary issues in VLSI interconnect. Of particular interest was, in one book, to cover both interconnect analysis and synthesis. Because of the increasing importance of interconnect in modern VLSI systems and the fact that these fields of research have gained a certain degree of maturity in recent years, we felt that the time was right for such a book. We hope that we have succeeded in providing a unique and timely perspective on the topic.

The work presented in this book grew out of research projects initiated at both the University of California at San Diego and at Hewlett Packard Labs. Chapters 2 through 4 were developed largely as the product of graduate courses and research conducted at UCSD by Chung-Kuan Cheng. Chapter 5 embodies research conducted at HP Labs. Chapters 6 through 9 grew largely out of John Lillis' Ph.D. work at UCSD, his later work at UC Berkeley, and continuing work at the University of Illinois at Chicago.

We want to make clear that the book is by no means intended to be comprehensive. The absence of coverage of work by other researchers should by no means diminish their contributions. Several research groups have made significant contributions in the field and the reader is encouraged to investigate their works. Key contributors to progress in interconnect-oriented design automation include Jason Cong and Andrew Kahng (UCLA), Gabriel Robins (U. Virginia), Majid Sarrafzadeh (NWU), Martin Wong (UT Austin), Margaret Marek-Sadowska (UCSB), Wayne Dai (UCSC), Larry Pileggi (CMU), Sachin Sapatnekar (U. Minnesota), Massoud Pedram (USC), Eby Friedman (U. Rochester), Kurt Antreich (Technical Univ. Munich), Pak Chan (UCSC), Jun-Dong Cho (Sungkyunkwan Univ.), Cheng-Kok Koh (Purdue), Xianlong Hong (Tsinghua Univ), Steve Kang (UIUC), C.L. Liu (Tsing Hua Univ.), Tatsuo Ohtsuki (Waseda), Takayasu Sakurai (Tokyo Univ.), Jacob White (MIT), CK Wong (Chinese Univ. Hong Kong), and Dian Zhou (UNCC).

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Edition details

• Publisher: Wiley-Interscience
• Publication date: 1999
• Language: English
• ISBN 10: 0471293660
• ISBN 13: 9780471293668
• Binding: Hardcover
• Edition number: 1
• Number of pages: 280