VCS verified data transactions on SoC bus using AMBA AXI-04 protocol: IP protocol for System-on-Chip Communication - Softcover
AMBA AXI-04 is an IP protocol which supports 16, masters and slaves interfacing. AMBA AXI-04 system consists of master, slave and interconnect. The system consists of five channels namely write address channel, write data channel, read address channel, read data channel, and write response channel. The AXI-04 update to AXI-03 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI-04 also includes information on the interoperability of components. The work aims to design master, slave and interconnect modules according to AMBA AXI-04 protocol, modelled in Verilog HDL. The simulation results for read and write operation of address and data are shown in VCS tool. The master and slave components have an interface with the test layer which provides necessary stimulus. This test layer is built exclusively to initiate the transaction and provide the meaningful inputs to master and slave. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation the module takes 160ns and for single write operation 565ns.
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Shaila S Math received M.Tech degree in VLSI from Visvesvaraya Technological University, India. She has published one national, international journal, and a IEEE conference paper. She is currently working as Assistant Professor in BMS Institute of Technology, Bangalore, India. She has been awarded with student IEEE membership as a best student.
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- PublisherLAP LAMBERT Academic Publishing
- Publication date2012
- ISBN 10 3659177903
- ISBN 13 9783659177903
- BindingPaperback
- Number of pages116
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VCS verified data transactions on SoC bus using AMBA AXI-04 protocol
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ISBN 10: 3659177903
ISBN 13: 9783659177903
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Book Description Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -AMBA AXI-04 is an IP protocol which supports 16, masters and slaves interfacing. AMBA AXI-04 system consists of master, slave and interconnect. The system consists of five channels namely write address channel, write data channel, read address channel, read data channel, and write response channel. The AXI-04 update to AXI-03 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI-04 also includes information on the interoperability of components. The work aims to design master, slave and interconnect modules according to AMBA AXI-04 protocol, modelled in Verilog HDL. The simulation results for read and write operation of address and data are shown in VCS tool. The master and slave components have an interface with the test layer which provides necessary stimulus. This test layer is built exclusively to initiate the transaction and provide the meaningful inputs to master and slave. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation the module takes 160ns and for single write operation 565ns. 116 pp. Englisch. Seller Inventory # 9783659177903
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VCS verified data transactions on SoC bus using AMBA AXI-04 protocol : IP protocol for System-on-Chip Communication
Published by
LAP Lambert Academic Publishing
(2012)
ISBN 10: 3659177903
ISBN 13: 9783659177903
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Book Description Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - AMBA AXI-04 is an IP protocol which supports 16, masters and slaves interfacing. AMBA AXI-04 system consists of master, slave and interconnect. The system consists of five channels namely write address channel, write data channel, read address channel, read data channel, and write response channel. The AXI-04 update to AXI-03 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI-04 also includes information on the interoperability of components. The work aims to design master, slave and interconnect modules according to AMBA AXI-04 protocol, modelled in Verilog HDL. The simulation results for read and write operation of address and data are shown in VCS tool. The master and slave components have an interface with the test layer which provides necessary stimulus. This test layer is built exclusively to initiate the transaction and provide the meaningful inputs to master and slave. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation the module takes 160ns and for single write operation 565ns. Seller Inventory # 9783659177903
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VCS verified data transactions on SoC bus using AMBA AXI-04 protocol: IP protocol for System-on-Chip Communication
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ISBN 10: 3659177903
ISBN 13: 9783659177903
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VCS verified data transactions on SoC bus using AMBA AXI-04 protocol: IP protocol for System-on-Chip Communication
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VCS verified data transactions on SoC bus using AMBA AXI-04 protocol
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Book Description Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Math Shaila S.Shaila S Math received M.Tech degree in VLSI from Visvesvaraya Technological University, India. She has published one national, international journal, and a IEEE conference paper. She is currently working as Assistant P. Seller Inventory # 5137298
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Vcs Verified Data Transactions On Soc Bus Using Amba Axi-04 Protocol: Ip Protocol For System-On-Chip Communication
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Book Description Paperback. Condition: Brand New. 116 pages. 8.66x5.91x0.27 inches. In Stock. Seller Inventory # zk3659177903
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