Creating Assertion-Based IP (Integrated Circuits and Systems) - Hardcover

Foster, Harry D.; Krolnik, Adam C.

Hardcover

ISBN 10: 0387366415 ISBN 13: 9780387366418

Publisher: Springer, 2007

Synopsis

This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions

Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. This is the first book published on this subject.

About this title

Product Description:

Creating Assertion-based IP This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning and is the first book published on this subject. Full description

Synopsis:

A project's functional verification testplan is the specification for the verification process. Developing this testplan usually involves the entire engineering team (architects, designers, and verification engineers). In general, the verification testplan defines exactly what functionality will be verified, how it will be verified (the verification strategy and resource allocation), and when the verification process is complete (for example, metrics for measuring progress or completion criteria). Without a verification testplan, it is unlikely that a verification team will achieve first-time verification success in both schedule and quality. Given that today's ASIC design flows often involve aggressive development schedules combined with limited verification resources, it is critical for the verification team to plan an appropriate verification solution that effectively targets each verification challenge.

However, while the process of simulation-based testplanning is well understood in a traditional verification environment, the process of formal-based testplanning is generally not well understood due to the lack of industry formal experience and published formal-based testplanning guidelines. As verification teams consider the option of integrating functional formal verification tools into their flow, the lack of a formal-based testplan often results in ad hoc verification results, with a questionable return on investment. This testplanning is critical in projects with a fixed time and resource budget for all verification activities. This book well presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. Note that there are many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of the discuss the important process of testplanning and using these languages to create verification IP. This will be the first book published on this subject.

About this edition

• Publisher: Springer
• Publication date: 2007
• ISBN 10: 0387366415
• ISBN 13: 9780387366418
• Binding: Hardcover
• Number of pages: 336